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Addressing Modes of 68000 processor


Immediate mode: The operand is contained in the instruction. Three sizes of operands can be specified byte, word and long word.
Absolute mode: The absolute address of an operand is given in the instruction, following the OP-code. There are two versions of this mode- long and short. In the long mode, a 24 bit address is specified explicitly. In the short mode, a 16 bit value is given in the instruction to be used as the low- order 16 bits of an address. The sign bit of this value is extended to provide the high order eight bits of address.
Register mode:  The operand is in a processor register specified in the instruction. 
Register Indirect mode: The effective address of the operand is in an address register, An, specified in the instruction. 
Autoincrement mode: The effective address of the operand is in an address register, An, specified in the instruction. After the operand is accessed, the contents of An, are incremented by 1,2 or 4, depending on whether a byte, a word or a long word operand. 
Autodecrement mode: The contents of an address register, An, specified in the instruction are decremented by 1,2 or 4, depending on whether a byte, a word or a long word operand. The effective address of the operand is the decremented contents of An. 
Basic Index mode: A 16- bit signed offset and an address register, An, are specified in the instruction. The sum of this offset and contents of An is the effective address of the operand 
Full Index mode: An 8- bit signed offset and an address register, An, and an index register Rk (either an address or data register) are specified in the instruction. The effective address of the operand is the sum of this offset and contents of register An & Rk. 
Basic relative mode:  A 16- bit signed offset and program counter (PC) are specified in the instruction. The sum of this offset and contents of PC is the effective address of the operand.  
Full relative mode:  A 8- bit signed offset, program counter (PC) and an index register Rk(either an address or data register) are specified in the instruction. The effective address of the operand is the sum of this offset and contents of register PC & Rk.

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